1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having a dynamic memory cell requiring a refresh operation in order to retain data therein.
2. Description of the Related Art
A semiconductor memory device (DRAM) using a dynamic memory cell as a storage element performs a refresh operation periodically, because the memory cell loses stored data as time elapses. When a synchronous dynamic RAM (SDRAM) is taken as an example, there are refresh operations executed in accordance with an external command (auto refreshing) and refresh operation periodically executed at a timing generated internally (self refreshing). The auto refreshing is executed in accordance with an input command in a state where the DRAM is activated. In the auto refreshing, the refresh operation is inserted between a write operation and a read operation, and thus a higher speed is required for the refresh operation. The self refreshing is performed at a timing generated inside the DRAM in a stand-by mode. In the self refreshing, write and read operations are not performed, and only the refresh operation is performed in periodical intervals.
In the auto refreshing, when a refresh command is input, a certain row address is selected, and the refresh operation is executed. At this stage, with respect to the row address, an address needs not be designated from the outside since a refresh counter provided in the internal of the DRAM automatically generates a refresh address. In order to retain data, the auto refreshing needs to be executed for a number of times corresponding to the number of row addresses within a specified time of the refresh period. For example, in case of 8192/64 ms, the auto refreshing is necessary for 8192 times within 64 ms. When the auto refreshing ends, the DRAM automatically returns to an idle mode.
The self refreshing is carried out in the mode where power consumption of the device is controlled to a lower value by deactivating the clock and allowing the device to assume a stand-by mode. The self refreshing is automatically carried out in the internal of the DRAM based on a timing of the refresh operation, the timing being generated by using the refresh counter in the DRAM.
In the auto refreshing, it is sufficient to satisfy the data retention time. A tRAS period (tRAS=Active to precharge command period: activated period of a cell array for access) during the auto refreshing is specified by tRASmin as a specification. On the other hand, during the self refreshing, there is a case where the data retention time equal to or longer than the tRASmin specified in the specification is needed by extending the refresh period due to the necessity to control the average current to a lower value. For this reason, the auto refreshing and the self refreshing are desired to have different time lengths for the tRAS period. However, in a related technique for the semiconductor device, since a signal (RASB signal) for activating the DRAM array is generated in the same signal path during the auto refreshing and during the self refreshing, there has been a case where the tRAS periods of the auto refreshing and the self refreshing are set at the same time length. In this case, there has been a problem that the tRAS period that provides a rewrite period of a memory cell is excessively short and a restoring level is insufficient in the self refreshing.
A technique that resolves the above problem is described in Patent Publication JP-2001-283586-A. FIG. 9 shows the circuit configuration of a section for generating an RASB signal in the semiconductor memory device described in JP-2001-283586-A. A NOR gate 201 and a NOR gate 202 in combination configures a set-reset flip-flop. RF_cmd signal for instructing a refresh operation is input to one of two inputs to the NOR gate 201. When the RF_cmd rises to H-level to instruct the refresh operation, the output RASB of the NOR gate 201 falls to L-level and the RASB signal is activated.
RTO signal is used for deactivation of the activated RASB signal. The RTO is input to one of two inputs of the NOR gate 202 configuring the flip-flop. Signal paths of the RTO include two paths, i.e., a signal path (signal path A) passing through a transistor 204 and a signal path (signal path B) passing through a transistor 205 and a delay gate 206. A signal obtained by inverting, in an inverter 203, a SR_EN signal showing whether or not the refresh operation is the self refreshing is input to a gate of the transistor 204, and the SR_EN signal is input in a gate of the transistor 205. During the auto refreshing, the transistor 204 is turned ON to select the signal path A. During the self refreshing, the transistor 205 is turned ON to select the signal path B.
FIG. 10 shows the circuit configuration of a part in relation to generation of the RTO node used in the RASB control circuit 200 shown in FIG. 9. A NAND gate 213 outputs NAND of a signal obtained by inverting the RASB signal in an inverter 211 and a signal obtained by delaying the output of the inverter 211 in a delay gate 212 by a delay time td_rto. An inverter 214 inverts the output of the NAND gate 213 and outputs the inverted output as the RTO node. After the RASB signal falls from H-level to L-level, the RTO node rises from L-level to H-level at a time instant delayed by the delay time td_rto of the delay gate 212 from the timing of fall of the RASB signal. In addition, the RTO node falls to L-level in accordance with a rise of the RASB signal from L-level to H-level.
FIG. 11 shows a timing chart showing the waveform of each part of the circuit shown in FIG. 9. The SR_EN signal is fixed to L-level for a period when the auto refreshing is executed. In the RASB control circuit 200, only the transistor 204 is turned ON out of the transistors 204 and 205 shown in FIG. 9, and the signal path A is selected as a signal path to the RTO node. The RASB signal is deactivated (H-level) at the beginning. When a one-shot pulse is applied to the RF_cmd, the output of the NOR gate 201, that is, the RASB signal, falls from H-level to L-level, and the RASB signal is activated.
When the RASB signal falls from H-level to L-level, one of inputs of the NAND gate 213 (FIG. 10) of the RTO generation section immediately rises to H-level, and the other input rises to H-level after the lapse of the delay time td_rto of the delay gate 212. When both of the inputs of the NAND gate 213 become H-level, the RTO node rises from L-level to H-level. The input PRE node of the NOR gate 202 is connected to the RTO node via the transistor 204, the level thereof rises from L-level to H-level in accordance with a level change of the RTO node.
When the RTO node (PRE node) rises to H-level, the output of the NOR gate 202 falls to L-level. In this manner, both inputs of the NOR gate 201 assume L-level, and the RASB signal rises from L-level to H-level. When the RASB signal rises to H-level, the output of the NAND gate 213 (FIG. 10) rises to H-level, and the RTO node falls to L-level. During the auto refreshing, a rising edge of the RTO node and a rising edge in the PRE node temporarily coincide with each other, and the tRAS is defined by a period from a falling edge of the RASB signal to the rising edge of the RTO (the rising edge of the RASB signal subsequent thereto).
On the other hand, in the period of executing the self refreshing, the SR_EN signal is fixed at H-level. By the SR_EN signal being fixed at H-level, only the transistor 205 is turned ON out of the transistors 204 and 205, and the signal path B is selected as the signal path to the RTO node. The RASB signal falls to L-level by a one-shot pulse in the RF_cmd, and thereafter the RTO node rises to H-level at a time instant delayed by the delay time td_rto of the delay gate 212. Operation up to this stage is the same as the operation during the auto refreshing.
During the self refreshing, since the signal path B is selected as a signal path to the input of the NOR gate 202, the PRE node rises to H-level at a time instant delayed by the delay time td of the delay gate 206 after the RTO rises to H-level. As the PRE node rises to H-level, the RASB signal rises to H-level, and thereafter, the RTO node falls to L-level. During the self refreshing, a signal change of the input PRE node is delayed by the delay time td from the signal change of the RTO node, and the tRAS is defined by a period from a falling edge of the RASB signal to a rising edge of the RASB signal driven by the rise of the PRE node.
The tRAS period (tRAS_sr) during the self refreshing is longer than the tRAS period (tRAS_ref) during the auto refreshing by the delay time td of the delay gate 206. For this reason, during the self refreshing, an L-level period (activated period) of the RASB signal is longer by the delay time td, and the selected period of a word line is extended. In this manner, a tRAS period corresponding to length of a cycle of the refreshing can be obtained during the auto refreshing and during the self refreshing, and appropriate driving time and restoring level can be obtained in both the auto refreshing and the self refreshing.
In the conventional semiconductor memory device, a delay gate is used, and a tRAS period is specified by the delay time of the delay gate. The delay time of the delay gate is easily affected by the ambient temperature and a process fluctuation, and there is a problem in that the tRAS period is difficult to control at an appropriate value. In addition, the generation circuit for the RASB signal is normally allocated in the vicinity of a memory cell, and is necessary for each bank. The enable signal (SR_EN signal) of the self refreshing for switching a signal path to RTO node needs to be allocated to a generation part of the RASB signal, and there is a problem in that the signal path is complicated due to increase in the number of wires. In addition, there is also a problem in that the circuit scale is increased due to provision of the delay gate.